NPUHE_PMCNTENSET

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Interpret as NPUHE_PMCNTENSET

EVENT_CNT_3=Val_0x0, EVENT_CNT_2=Val_0x0, EVENT_CNT_0=Val_0x0, CYCLE_CNT=Val_0x0, EVENT_CNT_1=Val_0x0

Performance Monitor Count Enable Set Register

EVENT_CNT_0	Enable PMU event counter 0. 0 (Val_0x0): When read, it means the event counter is disabled. When written, it has no effect. 1 (Val_0x1): When read, it means the event counter is enabled. When written, it enables the event counter.
EVENT_CNT_1	Enable PMU event counter 1. 0 (Val_0x0): When read, it means the event counter is disabled. When written, it has no effect. 1 (Val_0x1): When read, it means the event counter is enabled. When written, it enables the event counter.
EVENT_CNT_2	Enable PMU event counter 2. 0 (Val_0x0): When read, it means the event counter is disabled. When written, it has no effect. 1 (Val_0x1): When read, it means the event counter is enabled. When written, it enables the event counter.
EVENT_CNT_3	Enable PMU event counter 3. 0 (Val_0x0): When read, it means the event counter is disabled. When written, it has no effect. 1 (Val_0x1): When read, it means the event counter is enabled. When written, it enables the event counter.
CYCLE_CNT	Enable PMU cycle counter. 0 (Val_0x0): When read, it means the cycle counter is disabled. When written, it has no effect. 1 (Val_0x1): When read, it means the cycle counter is enabled. When written, it enables the cycle counter.

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